1. Field
This invention relates to a data processing system and in particular to a data processing system having cache memory.
2. Related Art
In a data processing system, a frequently accessed data is transferred to a cache memory operating at higher speed than a main memory, whereby the number of times a data processing system accesses the main memory is decreased. Consequently, speeding up data processing of the data processing system is accomplished.
Generally, a part of the address of a data transferred to a cache memory in a main memory becomes the address in the cache memory. Thus, two data stored at different addresses in the main memory may be assigned the same address in the cache memory. In this case, only one of the two data is transferred from the main memory to the cache memory.
An n-way set associative system (where n is an integer of two or more) is adopted as one of systems for associating cache memory and main memory with each other to transfer a plurality of data assigned the same address in the cache memory to the cache memory. In the n-way set associative system, cache memory having n ways is used and a plurality of data assigned the same address in the cache memory are transferred to different ways. As a result, the possibility that a frequently accessed data will not be stored in the cache memory is decreased.
The n-way set associative system adopts a high-speed access mode for giving a high priority to high-speed operation or a low-power access mode for giving a high priority to power saving as a cache memory access mode. In the high-speed access mode, a data requested by a read instruction (which will be hereinafter referred to as “objective data”) is selected from among a plurality of data read from all ways. Thus, the objective data is acquired by accessing the cache memory once. However, in the high-speed access mode, a data is read from all ways and thus the power consumption of the data processing system is large.
In the low-power access mode, which way the objective data exists in is determined and then the determined way is accessed for reading data therefrom. To acquire the objective data, the low-power access mode needs to access the cache memory twice. Therefore, a larger number of clock cycles required for acquiring data are necessary for the low-power access mode as compared with the high-speed access mode. However, since a data is read only from the determined way, the low-power access mode enables the data processing system to less consume power as compared with the high-speed access mode.
JP-T-2004-519776 discloses a method of predicting which way the objective data is stored in and decreasing the number of ways from which the data is read, in order to accomplish the high-speed operation and low power consumption of a data processing system. However, in this method, when the prediction fails, the number of clock cycles and power consumption of the data processing system until the objective data is obtained increase.
A data processing system having a pipeline structure processes a data at high speed by concurrently executing a plurality of processes. Therefore, when a data read instruction and an instruction using the read data are executed successively, the read data is used in the processes executed concurrently and therefore it is desirable that the data processing system should adopt the high-speed access mode. However, when the read data is not used in the processes executed concurrently, the processing time of the data processing system in the low-power access mode is the same as that in the high-speed access mode. Therefore, the data read in a read instruction is not used in the instruction executed after the read instruction, it is desirable that the data processing system should adopt the low-power access mode.
As described above, when the data read in a data read instruction is not used in the instruction executed right after the read instruction, a problem of unnecessarily large power consumption occurs in the data processing system adopting the high-speed access mode. On the other hand, in the data processing system adopting the low-power access mode, when a data read instruction and an instruction using the read data are executed successively, the number of clock cycles required for data processing becomes larger than that in the high-speed access mode.